1. Field of the Invention
The present invention relates to an integrated circuit memory device, and more particularly, to a word line driver circuit for supplying a voltage that is higher than the power source voltage requiring an internal boost voltage, and a driving method thereof.
2. Description of the Related Art
In a typical semiconductor memory device that operates at a low voltage, a bootstrap circuit is used to apply a higher voltage than the operating voltage to the capacitor of a memory cell in order to increase the operating speed in reading or writing data. In other words, to prevent or substantially reduce errors in read or write operations, the voltage corresponding to data applied to a bit line is transferred to the capacitor of a memory cell without dropping the threshold voltage of the access transistor of the memory cell, or data stored in the capacitor is supplied to the bit line without dropping the threshold voltage of the access transistor.
A typical word line driver circuit uses a bootstrap circuit for applying a higher voltage than the power source voltage Vcc to a word line.
FIG. 1 illustrates a word line driver according to the prior art.
Referring to FIG. 1, a word line driver circuit according to the prior art includes four transistors N11, N12, N13 and N14, and control signals SWL_PD, SWL_PDb and SWL_DRV. SWL_PD is typically a column select signal and SWL_PDb is the logical inverse of SWL_PD.
In the word line driver circuit, an output signal MWL of a word line decoding circuit (not shown) is typically a row enable signal. The logical state of MWL is transferred to the gate of transistor N12 via transistor N11 that operates from the power source voltage Vcc at its gate. Transistor N12 is configured to transfer control signal SWL_DRV, having an active state voltage level of an external power source voltage Vpp that is a higher voltage than the power source voltage Vcc, to a word line SWL. The word line SWL is also connected to discharge transistor N14 which is operated by inverse control signal SWL_PDb.
During a stand-by mode before active operation of the word line driver, all control signals shown in FIG. 5, except inverse control signal SWL_PDb, are in an inactive state and are applied with a ground voltage level Vss. When a read or write operation starts, an output signal MWL of a word line decoding circuit is asserted with an active state voltage level of the power source voltage Vcc and is applied to the word line driver corresponding to the selected word line. A node voltage between transistor N11 and transistor N12 rises by the voltage level Vcc−Vth obtained by deducting a threshold voltage Vth of transistor N11 from the power source voltage Vcc. The control signal SWL_DRV is then asserted with the active state voltage level of the external power source voltage Vpp and the node voltage between transistor N11 and transistor N12 is boosted to Vcc−Vth+Vpp due to the capacitance between the drain and the gate of transistor N12. As a result, transistor N12 has a sufficient gate voltage Vcc−Vth+Vpp. Therefore, the voltage level Vpp of control signal SWL_DRV is supplied to the word line SWL without dropping the threshold voltage of transistor N12. An access transistor of the memory cell connected to the word line SWL operates by a word line enable signal as the external power source voltage Vpp, thus errors are prevented.
In the word line driver circuit described above, an additional boost circuit or pumping circuit is supplied to obtain a voltage Vpp that is higher than the power source voltage Vcc and the higher voltage is transferred to the word line through control signal SWL_DRV. The additional boost circuit or pumping circuit to generate a voltage Vpp higher than the power source voltage Vcc must be supplied. Thus the chip size becomes larger and the power consumption increases.
Another example of a word line driver circuit according to the prior art is disclosed in U.S. Pat. No. 5,774,392 to William F. Kraus, et. al., which is referred to in FIG. 2.
Referring to FIG. 2, a word line driver circuit according to the prior art employs a ferroelectric capacitor FC0.
The word line driver circuit is constructed of a self boosting circuit and has an advantage of boosting only a selected word line WL0. This has a disadvantage that the data of memory cells connected to non-selected word lines like WL1 may be interfered with by a floating voltage because the non-selected word lines attain a floating state.
If the gain of transistor N0 and transistor N1 is not precisely determined, the voltage level of word line WL0 boosted by ferroelectric capacitor FC0 may excessively increase the voltage level of node WLEN0′ when control signal BOOSTDRIVE is applied. Thus, there may be the case that the voltage level of word line WL0 becomes the same as the voltage level of control signal WLCLK due to transistor N1. In other words, the voltage level difference of word line WL0 is insufficient for the operation, and in the worst case, there may be the case that a word line cannot be boosted.